This invention is directed to digital computer systems, and more specifically to the interaction between peripheral I/O units and a central processor in the computer system.
The control of transfer of data between the storage of the central processing unit and peripheral I/O devices over an input/output bus, or interface, can take many forms. Among the forms of input/output control for the purpose of data transfer are, direct program instruction control for each transfer of data, the initiation of data transfers by a central processor after which subsequent data transfer is accomplished under control of the peripheral device without use of the central processor, and logic for handling interrupt requests from peripheral devices to inform the central processor of peripheral device status. Included in various of these concepts are control mechanisms for permitting peripheral devices to initiate interrupt handling in the central processor by directly informing the processor of the device and status requiring handling, or the interrupt request may require the central processor to initiate a polling signal to all attached devices, in series, to subsequently permit information to be transferred to the central processor identifying the device and status causing the interrupt.
In systems utilizing direct program control for each data transfer between a peripheral device and main storage, interfaces are usually provided which require, in response to the program instruction, the sequential transfer of device addresses commands, and/or data to the peripheral device.
In data processing systems which not only provide for direct program control data transfers, but also cycle steal data transfers, different forms of program instructions are normally required. Even if different forms of initiating instructions are not required, different forms of peripheral device control information are required, which must be recognized by the peripheral device control unit and handled differently. Therefore, each peripheral device control unit must have specialized logic. Further, if the input/output control system is also required to handle asynchronous requests for interrupt servicing by the processor, additional circuitry in the peripheral device control unit must be provided.
During cycle steal data transfer operations when a peripheral device control unit has been provided with sufficient information to initiate and control further use of the interface bus for controlling the storage unit independent of the processor, certain exceptional conditions may occur prior to completion of the data transfer requiring special handling by the central processor before re-initiating the data transfer.
Normally, input/output control systems which are adapted to handle direct program control, cycle steal, or interrupt request transfers on a common interface, must handle each of these situations exclusively on the interface bus, preventing any other form of request from being processed.
In prior systems, polling logic has been provided for responding to an unknown interrupt request which signals the priority of the interrupt request. I/O control logic responds with a serial poll signal combined with identification from the central processor of the priority of the interrupt request being polled, to cause selection by a proper peripheral device control unit for subsequent use of the interface bus. The priority interrupt request made by a peripheral device control unit can be modified by a central processor. However, in these prior systems, the modification of the priority level of a peripheral device control unit could only be accomplished when the device associated with the peripheral device control unit is not busy with some previous command. Further, prior art systems which combine cycle steal data transfers with interrupt request handling have been required to provide separate logic within a peripheral device control unit and input/output control logic of the central processor to poll for the two forms of communication required.
Prior systems which incorporate a serial poll signal for the purposes of selecting one of a plurality of peripheral device control units, all of which are requesting service, require use of logic within each peripheral device control unit to propagate the serial poll signal to succeeding devices. In these prior systems it is readily evident that if a particular peripheral device control unit, or device, were physically removed from the input/output bus, proper functioning of the poll propagation would not be possible.